Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select transistors, such as a source select transistor and a drain select transistor.
A “column” refers to a group of memory cells that are commonly coupled to a local data line, such as a local bit line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line. Each source select transistor is connected to a source line, while each drain select transistor is connected to a data line, such as column bit line.
Memory arrays are sometimes arranged in blocks of memory cells, e.g., where a block may be arranged in rows and columns of memory cells. For example, a block of memory cells may be a plurality of memory cells (e.g., a plurality of NAND strings) that may be erased at once. For example, such blocks may be referred to as erase blocks. Blocks may include error correcting code (ECC) data that is used by ECC techniques to detect errors and correct errors, e.g., by recovering data, when the blocks are being read.
Blocks are susceptible to failure, i.e., a failure to meet some performance criteria or exceeding some performance limit, such as error correcting code (ECC) failures (e.g. where the ECC cannot recover data or where a number of detected ECC errors exceeds a certain value), erase failures (e.g., where the block cannot be erased in a certain number of erase-verify cycles), program failures (e.g., where the block cannot be programmed in a certain number of program-verify cycles), etc., and may be permanently retired from use at the first occurrence of such a failure. However, such failures are sometimes erratic and retirement schemes that permanently retire blocks at the first occurrence of such a failure can lead to the premature permanent retirement of those blocks.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing block retirement schemes.